This invention relates to a logic LSI chip incorporating a memory array, and more particularly to an LSI having means for testing the LSI chip.
It has been considered difficult to prepare test patterns used for testing logic circuits including a memory part. To deal with the difficulty described above, a testing method has been proposed in which a scanning circuit capable of performing scan-in/scan-out operations for logic signals is provided for the purpose of testing. According to the proposed method, flip-flops constituting a memory part are directly controlled and monitored through external terminals. However, the proposed method is effective only when the memory part is constituted by flip-flops.
A method of level sensitive testing on a logic LSI chip having a memory array is disclosed in, for example, U.S. Pat. No. 4,074,851. The testing method disclosed therein utilizes the so-called scanning method, but it is not applicable for direct scan-in/scan-out of a memory array. Therefore, there still remains a problem that extreme difficulty is encountered for the preparation of test patterns that can be used for testing the entire logic circuit. Another example of such a testing method is disclosed in U.S. patent application Ser. No. 575,706 (filed on Jan. 31, 1984) which is a previous application filed by the same inventors of the present application.
On the other hand there has been proposed a method for solving such a problem. According to the proposed method, the individual memory elements of the memory array are replaced by flip-flops. Although the proposed method obviates the difficulty of preparation of test patterns, it has been defective in that an inevitable increase in the hardware due to replacement of the memory elements by the flip-flops results in an excessive increase in the size of the LSI chip.
The present invention eliminates the defects of these related arts and facilitates the testing by merely additionally providing a small number of logic elements.